? semiconductor components industries, llc, 2002 june, 2002 rev. 5 1 publication order number: mc100ep40/d mc100ep40 3.3v / 5vecl differential phase-frequency detector the mc100ep40 is a threestate phasefrequency detector intended for phaselocked loop applications which require a minimum amount of phase and frequency difference at lock. advanced design significantly reduces the dead zone of the detector. for proper operation, the input edge rate of the r and v inputs should be less than 5 ns. the device is designed to work with a 3.3 v / 5 v power supply. when reference (r) and feedback (fb) inputs are unequal in frequency and/or phase the differential up (u) and down (d) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a vco. when reference (r) and feedback (fb) inputs are 80 ps or less in phase difference, the phase lock detect pin will indicate lock by a high state (v oh ). the v tx (v tr , v tr , v tfb , v tfb ) pins offer an internal termination network for 50 line impedance environment shown in figure 2. an external sinking supply of v cc 2 v is required on v tx pin(s). if you short the two differential v tr and v tr (or v tfb and v tfb ) together, you provide a 100 termination resistance that is compatible with lvds signal receiver termination. for more information on termination of logic devices, see and8020. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. for more information on phase lock loop operation, refer to and8040. special considerations are required for differential inputs under no signal conditions to prevent instability. ? maximum frequency > 2 ghz typical ? fully differential ? advanced high band output swing of 400 mv ? theoretical gain = 1.11 ? t rise 97 ps typical, f fall 70 ps typical ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 5.5 v ? 50 internal termination resistor marking diagram tssop20 dt suffix case 948e a = assembly location l = wafer lot y = year w = work week *for additional information, see application note and8002/d 100 ep40 alyw 20 1 device package shipping ordering information mc100ep40dt tssop20 75 units/rail mc100ep40dtr2 tssop20 2500 tape & reel 1 20 http://onsemi.com
mc100ep40 http://onsemi.com 2 figure 1. 20lead pinout (top view) 19 20 18 17 16 15 14 2 1 34567 13 8 12 9 11 10 dd uu v cc nc v ee vtfb fb fb v bb vtr figure 2. logic diagram u, u ecl up differential outputs d, d ecl down differential outputs fb, fb ecl feedback differential inputs r, r ecl reference differential inputs pld ecl phase lock detect function vtr ecl internal termination for r vtr ecl internal termination for r vtfb ecl internal termination for fb vtfb ecl internal termination for fb v bb reference voltage output v cc positive supply v ee negative supply nc no connect pin description warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. r u r u u a (v) fb d b b a reset reset c d a c d b reset reset c a b d d d v bb s r ff v cc pld v cc v ee vtfb rr vtr u r s ff d 50 50 50 50 v tr v tr v tfb fb v tfb pin function attributes characteristics value internal input pulldown resistor n/a internal input pullup resistor n/a esd protection human body model machine model charged device model > 4 kv > 400 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v0 @ 0.125 in transistor count 699 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc100ep40 http://onsemi.com 3 maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 20 tssop 20 tssop 140 100 c/w c/w jc thermal resistance (junctiontocase) std bd 20 tssop 23 to 41 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 100 128 160 100 130 160 110 140 170 ma v oh output high voltage (note 4) u, u , b, b pld 2225 1355 2350 1480 2475 1605 2275 1355 2400 1480 2525 1605 2300 1355 2425 1480 2550 1605 mv v ol output low voltage (note 4) 1775 1900 2025 1800 1925 2050 1825 1950 2075 mv v ih input high voltage (singleended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (singleended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential) (note 5) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current d d 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 4. all loading with 50 ohms to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100ep40 http://onsemi.com 4 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 7) 100 128 160 100 130 160 110 140 170 ma v oh output high voltage (note 8) 3925 4050 4175 3975 4100 4225 4000 4125 4250 mv v ol output low voltage (note 8) u, u , b, b pld 3475 3055 3600 3180 3725 3305 3500 3055 3625 3180 3750 3305 3525 3055 3650 3180 3775 3305 mv v ih input high voltage (singleended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (singleended) 3055 3375 3055 3375 3055 3375 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v ihcmr input high voltage common mode range (dif- ferential) (note 9) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current d d 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 7. for (v cc v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.3 v. 8. all loading with 50 ohms to v cc 2.0 volts. 9. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, necl v cc = 0 v; v ee = 5.5 v to 3.0 v (note 10) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 11) 100 128 160 100 130 160 110 140 170 ma v oh output high voltage (note 12) 1075 950 825 1025 900 775 1000 875 750 mv v ol output low voltage (note 12) u, u , b, b pld 1525 1945 1400 1820 1275 1695 1500 1945 1375 1820 1250 1945 1475 1945 1350 1820 1225 1945 mv v ih input high voltage (singleended) 1225 880 1225 880 1225 880 mv v il input low voltage (singleended) 1945 1625 1945 1625 1945 1625 mv v bb output voltage reference 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage common mode range (differential) (note 13) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current d d 0.5 150 0.5 150 0.5 150 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. input and output parameters vary 1:1 with v cc . 11. for (v cc v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.3 v. 12. all loading with 50 ohms to v cc 2.0 volts. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100ep40 http://onsemi.com 5 ac characteristics v cc = 0 v; v ee = 3.0 v to 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 14) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 3. f max /jitter) > 2 > 2 > 2 ghz t plh , t phl propagation delay to fb to d/u output differential r to d/u 400 525 700 410 550 750 450 575 775 ps t jitter cycletocycle jitter (see figure 3. f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input voltage swing (differential) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times q, q (20% 80%) 60 85 130 75 110 150 80 120 160 ps 14. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 ohms to v cc 2.0 v. 0 100 200 300 400 500 600 700 800 0 500 1000 1500 2000 2500 3000 3500 figure 3. f max /jitter frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) ?? ?? ????????????? ????????????? (jitter) v tt = v cc 2.0 v figure 4. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt
mc100ep40 http://onsemi.com 6 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices and8040 phase lock loop operation for an updated list of application notes, please see our website at http://onsemi.com.
mc100ep40 http://onsemi.com 7 package dimensions tssop20 dt suffix plastic tssop package case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t
mc100ep40 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100ep40/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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